1. Field of the Invention
The present invention relates to a semiconductor memory cell, particularly, to a memory cell used in, for example, a dynamic random access memory (DRAM).
2. Description of the Related Art
FIG. 1 shows a memory cell widely used nowadays in a DRAM. As shown in the drawing, the memory cell comprises a MOS (insulated gate) transistor Q acting as a transfer gate, which is connected to a word line WL and a bit line BL, and a capacitor C for data storage having a capacitor plate potential VPL connected to one end thereof.
To more highly integrate DRAM cells to thereby reduce the unit cost per bit of the memory cell, one of the inventors of the invention has proposed, in U.S. application Ser. No. 687,687, cascade gate type semiconductor memory cells shown in FIGS. 4 and 6.
The DRAM cell shown in FIG. 4 comprises a cascade gate including a plurality of cascade-connected MOS transistors Q1-Q4 and having one end connected to a read/write node N1, and a plurality of capacitors C1-C4 for data storage connected respectively to said MOS transistors Q1-Q4. In the semiconductor memory cell, the MOS transistors Q1-Q4 are sequentially turned on or off in a predetermined order so as to sequentially read data stored in the capacitors C1-C4 onto the read/write node N1 which is connected to a bit line in the order mentioned, and the read-out write-in data can be sequentially written into the capacitors C4-C1 from the node N1 in the order mentioned.
The DRAM cell shown in FIG. 6 is similar that shown in FIG. 4 except that is further incorporates a second node N2 and a MOS transistor Q5 connected between the transistor Q4 and node N2. Also in the DRAM cell of FIG. 6, by turning on or off the transistors Q1-Q5 in a predetermined order so as to sequentially read data stored in the capacitors C1-C4 onto the node N1 in the order mentioned, and the data can be sequentially written into the capacitors C1-C4 from the node N2 in the order mentioned.
The above described cascade gate type memory cells shown in FIGS. 4 and 6 can store data of a plurality of bits in units of one bit. Thus, as compared with a conventional DRAM consisting of an array of one transistor-one capacitor type cells, leading to a remarkably highly integrated DRAM can be formed of an array of memory cells of the cascade gate type, thereby much reducing the unit cost per bit of the memory cell, since only one contact is required to connect a plurality of cells or bits to a bit line.
By the way, when data stored in the capacitors C1-C4 is sequentially read onto the node N1, a capacitor which has been accessed (e.g., C1) remains connected electrically to the node N1. Therefore, when another capacitor (e.g., C2) is accessed, part of the readout charges are distributed to the above described capacitor C1. In this case, if the capacitors C1-C4 have same capacitance, the voltage variation of the node N1 which occurs while the capacitors C2-C4 are successively accessed is gradually reduced compared with the voltage variation of the node N1 which occurs while the capacitor C1 is accessed. In the extreme case, when the capacitor C4 is accessed, part of the read-out charges are distributed to the capacitors C1-C3, and the voltage variation of the node N1 is extremely reduced, so that data are in danger of being erroneously read out.